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? semiconductor components industries, llc, 2011 march, 2011 ? rev. 3 1 publication order number: ncv8508b/d ncv8508b 5.0 v and 3.3 v, 250 ma ldo with watchdog and reset the ncv8508b is a precision micropower low dropout (ldo) voltage regulator. the part contains many of the required features for powering microprocessors. its robustness makes it suitable for severe automotive environments. in addition, the ncv8508b is ideal for use in battery operated, microprocessor controlled equipment because of its extremely low quiescent current. features ? output voltage: 5.0 v and 3.3 v ? 3.0% output voltage ? i out up to 250 ma ? quiescent current independent of load ? micropower compatible control functions: ? wakeup ? watchdog ? reset ? low quiescent current (100 a typ) ? protection features: ? thermal shutdown ? short circuit ? 45 v operation ? ncv prefix for automotive and other applications requiring site and change controls ? aec qualified ? ppap capable ? these are pb ? free devices figure 1. application circuit c1* v out gnd v in wdi ncv8508b 1.0 f i/o i/o reset reset 0.1 f c2 microprocessor delay r delay 60 k v bat *c1 required if regulator is located far from power supply filter. v dd wakeup mra4004t3 see detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. ordering information marking diagrams xx, x = voltage option 5.0 v (xx = 50, x = 5) 3.3 v (xx = 33, x = 3) y = timing option (see page 4 for more details) 1 (delay time = 3 ms @ r delay = 60k) 2 (delay time = 9 ms @ r delay = 60k) a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or =pb ? free package http://onsemi.com d 2 pak ? 7 ds suffix case 936ab 508ybx alyw 1 8 so ? 8 ep pd suffix case 751ac 1 8 v8508ybxx awlywwg 1
ncv8508b http://onsemi.com 2 pin connections 1 d 2 pak ? 7 tab = gnd lead 1. v out 2. v in 3. wdi 4. gnd 5. wakeup 6. reset 7. delay v out sense gnd delay v in wdi wakeup reset 1 8 so ? 8 ep package pin description package pin # pin symbol function d 2 pak ? 7 so ? 8 ep 1 4 v out regulated output voltage 3.0%. 2 5 v in supply voltage to the ic. 3 6 wdi cmos compatible input lead. the watchdog function monitors the falling edge of the incoming signal. 4 2 gnd ground connection. 5 7 wakeup cmos compatible output consisting of a continuously generated signal used to ?wake up? the microprocessor from sleep mode. 6 8 reset cmos compatible output lead reset goes low whenever v out drops by more than 7.0% from nominal, or during the absence of a correct watchdog signal. 7 1 delay buffered bandgap voltage used to create timing current for reset and wakeup from r delay. ? ? nc no connection. ? 3 sense kelvin connection which allows remote sensing of the output voltage for improved regulation. connect to v out if remote sensing is not required. ? epad epad connect to ground potential or leave unconnected.
ncv8508b http://onsemi.com 3 figure 2. block diagram ? + + ? wakeup circuit timing circuit falling edge detect watchdog circuit thermal shutdown current limit charge pump bandgap reference v in reset v out wakeup wdi delay ? + 1.25 v 11 v internally connected on 7 lead d 2 pak sense maximum ratings rating value unit input voltage, v in (dc) ? 0.3 to 45 v peak transient voltage (46 v load dump @ v in = 14 v) 60 v output voltage, v out ? 0.3 to 18 v esd susceptibility: human body model machine model charged device model 2.0 200 1.0 kv v kv logic inputs/outputs (reset , wdi, wakeup) ? 0.3 to +7.0 v operating junction temperature, t j ? 40 to150 c storage temperature range, t s ? 55 to +150 c peak reflow soldering temperature: reflow: (note 1) 260 peak (note 2) c moisture sensitivity level: d2pak ? 7 so ? 8ep 3 2 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. 2. ? 5 c/+0 c allowable conditions. thermal characteristics see package thermal data section (page 11)
ncv8508b http://onsemi.com 4 electrical characteristics ( ? 40 c t j 125 c; 6.0 v v in 28 v, 100 a i out 150 ma, c 2 = 1.0 f, r delay = 60 k; unless otherwise specified.) characteristic test conditions min typ max unit output output voltage 5.0 v ? 4.85 5.00 5.15 v output voltage 3.3 v ? 3.201 3.3 3.399 v dropout voltage (v in ? v out ) 5.0 v i out = 150 ma. note 3 ? 450 900 mv load regulation v in = 14 v, 100 a i out 150 ma ? 5.0 30 mv line regulation 6.0 v v in 28 v, i out = 5.0 ma ? 5.0 50 mv current limit ? 250 400 ? ma thermal shutdown guaranteed by design 150 180 210 c quiescent current v in = 12 v, i out = 150 ma, (see figure 6) ? 100 150 a reset threshold 5.0 v ? 4.50 4.65 4.80 v threshold 3.3 v ? 2.970 3.069 3.168 v output low r load = 10 k to v out , v out 1.0 v r load = 5.1 k to v out , v out 1.0 v ? 0.2 0.4 0.4 0.8 v output high r load = 10 k to gnd r load = 5.1 k to gnd v out ? 0.5 v out ? 1.0 v out ? 0.25 v out ? 0.5 ? v delay time ncv85081b v in = 14 v, r delay = 60 k, i out = 5.0 ma v in = 14 v, r delay = 120 k, i out = 5.0 ma 2.0 ? 3.0 6.0 4.0 ? ms ms delay time ncv85082b v in = 14 v, r delay = 60 k, i out = 5.0 ma v in = 14 v, r delay = 120 k, i out = 5.0 ma 6.0 ? 9.0 18 12.0 ? ms ms watchdog input threshold high ? 70 ? ? %v out threshold low ? ? ? 30 %v out hysteresis ? ? 100 ? mv input current wdi = 6.0 v ? 0.1 +10 a pulse width 50% wdi falling edge to 50% wdi rising edge and 50% wdi rising edge to 50% wdi falling edge, (see figure 5) 5.0 ? ? s wakeup output (v in = 14 v, i out = 5.0 ma) wakeup period ncv85081b see figures 4 and 5, r delay = 60 k see figures 4 and 5, r delay = 120 k 18 ? 25 50 32 ? ms ms wakeup period ncv85082b r delay = 60 k r delay = 120 k 54 ? 75 150 96 ? ms ms wakeup duty cycle nominal see figure 3 45 50 55 % reset high to wakeup rising delay time ncv85081b r delay = 60 k, 50% reset rising edge to 50% wakeup edge r delay = 120 k (see figures 3 and 4) 9.0 ? 12.5 25 16 ? ms ms 3. measured when the output voltage has dropped 100 mv from the nominal value. (see figure 12) 4. current drain on the delay pin directly affects the delay time, wakeup period, and the reset to wakeup delay time.
ncv8508b http://onsemi.com 5 electrical characteristics ( ? 40 c t j 125 c; 6.0 v v in 28 v, 100 a i out 150 ma, c 2 = 1.0 f, r delay = 60 k; unless otherwise specified.) characteristic unit max typ min test conditions wakeup output (v in = 14 v, i out = 5.0 ma) reset high to wakeup rising delay time ncv85082b r delay = 60 k, 50% reset rising edge to 50% wakeup edge r delay = 120 k 27 ? 37.5 75 48 ? ms ms wakeup response to watchdog input 50% wdi falling edge to 50% wakeup falling edge ? 0.1 5.0 s wakeup response to reset 50% reset falling edge to 50% wakeup falling edge v out = v out_nom ? > 90% of v out_nom ? 0.1 5.0 s output low r load = 10 k to v out , v out 1.0 v r load = 5.1 k to v out , v out 1.0 v ? 0.2 0.4 0.4 0.8 v output high r load = 10 k to gnd r load = 5.1 k to gnd v out ? 0.5 v out ? 1.0 v out ? 0.25 v out ? 0.5 ? v delay output voltage i delay = 50 a. note 4 ? 1.25 ? v 3. measured when the output voltage has dropped 100 mv from the nominal value. (see figure 12) 4. current drain on the delay pin directly affects the delay time, wakeup period, and the reset to wakeup delay time.
ncv8508b http://onsemi.com 6 timing diagrams watchdog pulse width v in reset wakeup wdi v out wakeup duty cycle = 50% power up microprocessor sleep mode normal operation with varying watchdog signal reset high to wakeup delay time por figure 3. power up, sleep mode and normal operation figure 4. error condition: watchdog remains low and a reset is issued v in reset wakeup wdi v out por reset high to wakeup delay time reset delay time reset high to wakeup delay time wakeup period por reset wakeup wdi v out watchdog pulse width reset threshold por power down wakeup period figure 5. power down and restart sequence wdi pulse must occur with wakeup in low state for 50% duty cycle. reference figure 18 for occurrence of wdi with wakeup in high state.
ncv8508b http://onsemi.com 7 typical performance characteristics figure 6. quiescent current vs output current 0 80 output current (ma) 50 100 150 200 250 110 100 90 quiescent current a) ? 40 c +25 c +125 c 0 0 switching current (ma) 50 100 150 200 250 ? 700 v out transient (mv) ? 400 ? 300 ? 200 ? 100 100 f figure 7. load transient response ? 40 2 t j , temperature ( c) ? 20 0 140 10 por delay (ms) 9 8 7 6 5 4 3 20 40 60 80 100 120 figure 8. reset delay time vs junction temperature figure 9. reset delay time vs reset delay resistor 15 0 r delay (k ) 60 240 40 por delay (ms) 35 25 20 15 10 5 105 150 195 ? 40 0 t j , temperature ( c) 20 40 60 80 100 120 140 90 80 wakeup period (ms) 60 50 40 30 20 10 ? 20 0 figure 10. wakeup period vs junction temperature figure 11. wakeup period vs reset delay resistor 15 0 r delay (k ) 60 240 350 wakeup period (ms) 300 250 200 150 100 50 105 150 195 ? 500 ? 600 10 f 1.0 f ncv85081b ncv85081b ncv85081b ncv85081b t rise/fall = 1.0 s (switching current) 160 ncv85082b 30 ncv85082b 70 160 ncv85082b ncv85082b
ncv8508b http://onsemi.com 8 typical performance characteristics figure 12. dropout voltage vs output current figure 13. output voltage vs junction temperature, 5 v 0 dropout voltage (v) 0.0 output current (ma) 0.1 0.2 0.3 0.4 0.5 0.6 1.0 50 100 150 +25 c +125 c ? 40 c ? 40 output voltage (v) 4.90 t j , temperature ( c) 4.95 5.00 5.05 5.10 ? 20 0 40 20 60 80 100 120 140 160 v in = 14 v i out = 5.0 ma 200 250 0.7 0.8 0.9 figure 14. output voltage vs junction temperature, 3.3 v ? 40 output voltage (v) 3.20 t j , temperature ( c) 3.22 3.30 3.32 3.40 ? 20 0 40 20 60 80 100 120 140 160 v in = 14 v i out = 5.0 ma figure 15. output current vs input voltage 0 output current (ma) 0 input voltage (v) 40 60 80 100 120 140 160 20 23456 r l = 33 0.01 100 10 1 0 50 100 150 200 25 0 esr ( ) output current (ma) figure 16. output capacitor esr stable region c out = 1.0 f ? 100 f 1 0.1 3.24 3.26 3.28 3.34 3.36 3.38
ncv8508b http://onsemi.com 9 definition of terms dropout voltage: the input ? output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. input voltage: the dc voltage applied to the input terminals with respect to ground. line regulation: the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation: the change in output voltage for a change in load current at constant chip temperature. quiescent curr ent: the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current. ripple rejection: the ratio of the peak ? to ? peak input ripple voltage to the peak ? to ? peak output ripple voltage. current limit: peak current that can be delivered to the output. detailed operating description the ncv8508b is a precision micropower voltage regulator with very low quiescent current (100 a typical at 250 ma load). a typical dropout voltage is 450 mv at 150 ma for 5 v option. microprocessor control logic includes watchdog, wakeup and reset . this unique combination of extremely low quiescent current and full microprocessor control makes the ncv8508b ideal for use in battery operated, microprocessor controlled equipment in addition to being a good fit in the automotive environment. the ncv8508b wakeup function brings the microprocessor out of sleep mode. the microprocessor in turn signals its wakeup status back to the ncv8508b by issuing a watchdog signal. the watchdog logic function monitors an input signal (wdi) from the microprocessor. the ncv8508b responds to the falling edge of the watchdog signal which it expects at least once during each wakeup period. when the correct watchdog signal is received, a falling edge is issued on the wakeup signal line. reset is independent of v in and operates correctly to an output voltage as low as 1.0 v. a signal is issued in any of three situations. during power up, the reset is held low until the output voltage is in regulation. during operation, if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. finally, a reset signal is issued if the regulator does not receive a watchdog signal within the wakeup period. the reset pulse width, wakeup signal frequency, and wakeup delay time are all set by one external resistor, r delay . the delay pin is a buffered bandgap voltage (1.25 v). it can be used as a reference for an external tracking regulator as shown in figure 17. the regulator is protected against short circuit and thermal runaway conditions. the device runs through 45 volt transients, making it suitable for use in automotive environments. v out gnd v in ncv8508b 1.0 f 0.1 f delay v bat v in figure 17. application circuit cs8182 10 f 0.1 f 60 k gnd adj mra4004t3 v ref /enable 3.9 k 12 k 200 ma 5 v
ncv8508b http://onsemi.com 10 circuit description functional description to reduce the drain on the battery, a system can go into a low current consumption mode whenever it is not performing a main routine. the w akeup signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. the nominal output is a 5.0 (or 3.3 v) volt square wave (voltage generated from v out ) with a duty cycle of 50% at a frequency that is determined by a timing resistor, r delay . when the microprocessor receives a rising edge from the wakeup output, it must issue a w atchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. the first falling edge of the watchdog signal causes the wakeup to go low within 2.0 s (typ) and remain low until the next wakeup cycle (see figure 18). other watchdog pulses received within the same cycle are ignored (figure 3). during power up, reset is held low until the output voltage is in regulation. during operation, if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. after the reset delay, reset returns high. the watchdog circuitry continuously monitors the input watchdog signal (wdi) from the microprocessor. the absence of a falling edge on the watchdog input during one wakeup cycle will cause a reset pulse to occur at the end of the wakeup cycle. (see figure 4). the wakeup output is pulled low during a reset regardless of the cause of the reset . after the reset returns high, the wakeup cycle begins again (see figure 4). the reset delay time, wakeup signal frequency and reset high to w akeup delay time are all set by one external resistor r delay . wakeup period = (4.17 10 ? 7 )r delay reset delay time = (5.21 10 ? 8 )r delay reset high to wakeup delay time = (2.08 10 ? 7 )r delay resistor temperature coefficient and tolerance as well as the tolerance of the ncv8508b must be taken into account in order to get the correct system tolerance for each parameter. figure 18. wakeup response to wdi wakeup wdi wakeup response to wdi figure 19. wakeup response to reset (low voltage) wakeup response to reset reset wakeup
ncv8508b http://onsemi.com 11 recommend thermal data for d 2 pak ? 7 package parameter test conditions typical value units min ? pad board (note 5) 1? ? pad board (note 6) junction ? to ? lead (psi ? jl , jl ) 12 12 c/w junction ? to ? ambient (r ja , ja ) 84 48 c/w 5. 1 oz. copper, 118 mm 2 copper area, 0.062? thick fr4. 6. 1 oz. copper, 626 mm 2 copper area, 0.062? thick fr4. package construction with and without mold compound various copper areas used for heat spreading active area (red) times 2 (only showing 1/2 symmetry) figure 20. pcb layout and package construction for simulation
ncv8508b http://onsemi.com 12 table 1. d 2 pak 7 ? lead thermal rc network models 118 mm 2 626 mm 2 118 mm 2 626 mm 2 cu area cauer network foster network c?s c?s units tau tau units 1 8.6e ? 07 8.6e ? 07 w ? s/c 1.00e ? 07 1.00e ? 07 sec 2 3.6e ? 06 3.6e ? 06 w ? s/c 1.00e ? 06 1.00e ? 06 sec 3 1.4e ? 05 1.4e ? 05 w ? s/c 1.00e ? 05 1.00e ? 05 sec 4 1.4e ? 04 1.4e ? 04 w ? s/c 3.07e ? 04 3.07e ? 04 sec 5 6.4e ? 04 6.4e ? 04 w ? s/c 1.00e ? 03 1.00e ? 03 sec 6 1.1e ? 02 1.1e ? 02 w ? s/c 6.00e ? 03 6.00e ? 03 sec 7 3.0e ? 02 3.0e ? 02 w ? s/c 2.00e ? 02 2.00e ? 02 sec 8 4.9e ? 01 5.2e ? 01 w ? s/c 1.43e+00 1.43e+00 sec 9 4.8e ? 01 1.5e+00 w ? s/c 6.15e+00 3.82e+00 sec 10 6.9e ? 01 9.5e ? 01 w ? s/c 1.04e+02 9.68e+01 sec r?s r?s r?s r?s 1 0.147 0.147 c/w 0.090 0.090 c/w 2 0.301 0.301 c/w 0.194 0.194 c/w 3 0.603 0.603 c/w 0.614 0.614 c/w 4 2.733 2.733 c/w 1.200 1.200 c/w 5 1.178 1.178 c/w 2.600 2.600 c/w 6 1.369 1.366 c/w 0.100 0.100 c/w 7 0.272 0.270 c/w 1.700 1.700 c/w 8 14.820 7.855 c/w 0.100 0.100 c/w 9 6.055 2.741 c/w 6.944 5.181 c/w 10 56.834 30.488 c/w 70.770 35.902 c/w note: bold face items in the cauer network above, represent the package without the external thermal system. the bold face item s in the foster network are computed by the square root of time constant r(t) = 166 * sqrt(time(sec)). the constant is derived base d on the active area of the device with silicon and epoxy at the interface of the heat generation. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1 ? e ? t tau i
ncv8508b http://onsemi.com 13 ja vs copper spreader area 0 20 40 60 80 100 10 0 100 200 300 400 500 600 700 800 ja ( c/w) copper area (mm 2 ) figure 21. d 2 pak 7 ? lead ja as a function of the pad copper area including traces, board material 1 oz 2 oz 30 50 70 90 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) cu area 118 mm 2 , 1 oz cu area 626 mm 2 , 1 oz r(t) ( c/w) figure 22. d 2 pak 7 ? lead single pulse heating curve 0.1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse duration (sec) 1 r(t) ( c/w) single 50% duty cycle 20% 10% 5% 1% cu area 626 mm 2 , 1 oz cu figure 23. d 2 pak 7 ? lead thermal duty cycle curves on 1? spreader test board
ncv8508b http://onsemi.com 14 junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 24. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc ? product time constant; amplitudes are the resistances. ambient (thermal ground) figure 25. non ? grounded capacitor thermal ladder (?foster? ladder)
ncv8508b http://onsemi.com 15 recommend thermal data for soic ? 8 ep package parameter test conditions typical value units pad is soldered to pcb copper min ? pad board (note 7) 1? ? pad board (note 8) junction ? to ? lead (psi ? jl , jl ) 38 24 c/w junction ? to ? lead (psi ? jpad, jp ) 8.0 9.0 c/w junction ? to ? ambient (r ja , ja ) 126 64 c/w 7. 1 oz. copper, 54 mm 2 copper area, 0.062? thick fr4. 8. 1 oz. copper, 717 mm 2 copper area, 0.062? thick fr4. 8 ? soic ep half symmetry copper pad layout 25 x 25mm bottom view with mold compound top view with and without mold compound figure 26. internal construction of the package and pcb layout for multiple pad area
ncv8508b http://onsemi.com 16 table 2. soic 8 ? lead ep thermal rc network models 54 mm 2 717 mm 2 54 mm 2 717 mm 2 cu area cauer network foster network c?s c?s units tau tau units 1 2.7e ? 06 2.7e ? 06 w ? s/c 1.00e ? 06 1.00e ? 06 sec 2 1.1e ? 05 1.1e ? 05 w ? s/c 1.00e ? 05 1.00e ? 05 sec 3 3.2e ? 05 3.2e ? 05 w ? s/c 1.00e ? 04 1.00e ? 04 sec 4 1.3e ? 04 1.3e ? 04 w ? s/c 9.39e ? 04 9.39e ? 04 sec 5 1.8e ? 03 1.8e ? 03 w ? s/c 3.13e ? 03 3.13e ? 03 sec 6 7.9e ? 03 8.3e ? 03 w ? s/c 3.30e ? 02 3.30e ? 02 sec 7 2.5e ? 02 3.1e ? 02 w ? s/c 6.00e ? 01 6.00e ? 01 sec 8 1.4e ? 01 5.1e ? 01 w ? s/c 4.00e+00 4.00e+00 sec 9 4.1e ? 01 2.1e+00 w ? s/c 1.16e+01 4.83e+01 sec 10 1.6e+00 6.3e+01 w ? s/c 5.58e+01 2.37e+02 sec r?s r?s r?s r?s 1 0.474 0.474 c/w 0.282 0.282 c/w 2 1.086 1.086 c/w 0.610 0.610 c/w 3 3.011 3.010 c/w 1.929 1.929 c/w 4 5.883 5.874 c/w 5.825 5.825 c/w 5 1.944 1.911 c/w 2.700 2.700 c/w 6 4.655 4.264 c/w 3.000 3.000 c/w 7 21.431 15.678 c/w 15.000 15.000 c/w 8 40.130 9.238 c/w 11.494 7.797 c/w 9 23.392 18.454 c/w 34.982 20.473 c/w 10 24.381 3.581 c/w 50.566 5.953 c/w note: bold face items in the cauer network above, represent the package without the external thermal system. the bold face item s in the foster network are computed by the square root of time constant r(t) = 225 * sqrt(time(sec)). the constant is derived base d on the active area of the device with silicon and epoxy at the interface of the heat generation. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1 ? e ? t tau i
ncv8508b http://onsemi.com 17 ja vs copper spreader area 60 20 80 40 100 0 120 140 0 100 200 300 400 500 600 700 800 ja ( c/w) copper area (mm 2 ) figure 27. soic 8 ? lead ep ja as a function of the pad copper area including traces, board material 1 oz 2 oz 0.1 1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) cu area 54 mm 2 , 1 oz cu area 717 mm 2 , 1 oz r(t) ( c/w) figure 28. soic 8 ? lead ep single pulse heating curve 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) r(t) ( c/w) single 50% duty cycle 20% 10% 5% 1% cu area 717 mm 2 , 1 oz cu figure 29. soic 8 ? lead thermal duty cycle curves on 1? spreader test board
ncv8508b http://onsemi.com 18 junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 30. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc ? product time constant; amplitudes are the resistances. ambient (thermal ground) figure 31. non ? grounded capacitor thermal ladder (?foster? ladder)
ncv8508b http://onsemi.com 19 application notes calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 32) is: p d(max) [v in(max) v out(min) ]i out(max) (1) v in(max) i q where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . smart regulator i q control features i out i in figure 32. single output regulator with key performance parameters labeled v in v out } once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in data sheets of heatsink manufacturers.
ncv8508b http://onsemi.com 20 ordering information device output voltage timing option (r delay = 60 k ) package shipping ? ncv85081bds50g 5.0 v delay time = 3 ms wakeup period = 25 ms reset high to wakeup rising delay time = 12.5 ms d2pak 7 (pb free) 50 units / rail NCV85081BDS50R4G 5.0 v delay time = 3 ms wakeup period = 25 ms reset high to wakeup rising delay time = 12.5 ms d2pak 7 (pb free) 750 / tape & reel ncv85081bpd50r2g 5.0 v delay time = 3 ms wakeup period = 25 ms reset high to wakeup rising delay time = 12.5 ms so 8 ep (pb free) 2500 / tape & reel ncv85082bpd33r2g 3.3 v delay time = 9 ms wakeup period = 75 ms reset high to wakeup rising delay time = 37.5 ms so 8 ep (pb free) 2500 / tape & reel note: contact factory for other options. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8508b http://onsemi.com 21 package dimensions ? 8 ep case 751ac ? 01 issue b ?? ?? ?? h c 0.10 d e1 a d pin one 2 x 8 x seating plane exposed gauge plane 14 5 8 d c 0.10 a-b 2 x e b e c 0.10 2 x top view side view bottom view detail a end view section a ? a 8 x b a-b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 0 8 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc a1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* location exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 7.0 0.275 2.72 0.107
ncv8508b http://onsemi.com 22 package dimensions 0.539 d 2 pak ? 7 (short lead) case 936ab ? 01 issue b dim min max min max millimeters inches e 0.380 0.420 9.65 10.67 d 0.325 0.368 8.25 9.53 a 0.170 0.180 4.32 4.57 b 0.026 0.036 0.66 0.91 c2 0.045 0.055 1.14 1.40 e 0.050 bsc 1.27 bsc h 0.579 13.69 14.71 l1 a1 0.000 0.010 0.00 0.25 c 0.017 0.026 0.43 0.66 e d l1 c2 c b e e1 d1 h ??? 0.066 ??? 1.68 l 0.058 0.078 1.47 1.98 m l3 0.010 bsc 0.25 bsc 0 8 0 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions d and e do not include mold flash and gate protrusions. mold flash and gate protrusions not to exceed 0.005 maximum per side. these dimensions to be measured at datum h. 4. thermal pad contour optional within dimensions e, l1, d1, and e1. dimensions d1 and e1 establish a minimum mounting surface for the thermal pad. d1 0.270 ??? 6.86 ??? e1 0.245 ??? 6.22 ??? a dimensions: millimeters 0.424 7x 0.584 0.310 0.136 0.040 0.050 pitch soldering footprint* a1 l3 b h l m detail c seating plane gauge plane a 7x m a m 0.13 b e/2 b seating plane a a detail c view a ? a m a m 0.10 b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8508b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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